1. Field of the Invention
The present invention relates to methods for manufacturing semiconductor devices. More particularly, the present invention relates to a method for manufacturing a semiconductor device, wherein said method includes a step of forming an opening such as a contact hole and a succeeding heat treatment step such as a contact annealing for activating ion-implanted impurities in the bottom of the opening, and is advantageous for manufacture of a semiconductor device having a structure in which a diffusible material such as a dielectric material used in a capacitor may diffuse through such an opening due to heat during such heat treatment.
2. Description of the Related Art
In many cases, methods for manufacturing semiconductor devices require heat treatment after a step of forming openings. For example, in a method for manufacturing a semiconductor device which has an ordinary structure such as an LSI carrying a MOS transistor, supplemental-ion implantation for improving the junction properties and heat treatment such as at 800.degree. C. or higher for activating the implanted ions are required after the step of forming a contact hole on a diffusion layer of the transistor. During such heat treatment, diffusion through the contact hole into the inside of the semiconductor substrate frequently occurs due to heating. For example, in a structure having a capacitor, the composition of a dielectric material 2 (especially, ferroelectric material) as a component of a capacitor 3 may invade the semiconductor substrate 4 (silicon substrate) and a gate insulating film 5 (gate oxide film) through a contact hole as an opening 1, as shown in FIG. 5. The example shown in FIG. 5 is a FE (Ferro-Electric) RAM including a MOS transistor Tr and a capacitor 3, and especially, a capacitor 3 in which a ferroelectric material is used as a dielectric material 2. In a structure using such a ferroelectric material, diffusion of elements as components of the ferroelectric material through the opening 1 is a marked problem. Actually, although PZT (Pb--Zr--Ti-based materials) and SBT (Sr--Bi--Ta-based materials) are used as typical ferroelectric materials used in FE-RAMs, the component elements in these materials are vaporized at 800.degree. C., and especially, Bi had been reported as vaporizable even at 600.degree. C. Similar problems also may occur in DRAMs which include highly dielectric materials such as BST (Ba--Sr--Ti--O-based materials) and STO (Sr--Ti--O-based materials).
Although the diffusion pathway of a diffusible material 2 through such an opening 1 is not necessarily clear, the following manner as schematically shown in FIG. 5 with a dotted line and an arrowhead D is considered as predominant: The diffusible material 2 diffuses in an interlayer insulating film 63 (comprising silicon dioxide or the like) formed on a capacitor 3 so as to cover the capacitor 3, and then is vaporized to reach a diffusion layer 8. It may also partially invade a substrate 4 and a gate insulating film 5 by passing through the interlayer insulating film 63, externally or internally along the side wall of the opening 1, or along the interface between the side wall of the opening 1 and the atmospheric substances inside the opening.
Such diffusion can be disadvantageous since it may cause, for example, property change and reliability deterioration in transistors. Specifically, increase in junction leakage, reduction in gate breakdown voltage, and change in the threshold can be caused. As in VLSI and ULSI, semiconductor devices are manufactured with increasing fineness, giving them denser structures. Due to this, such unnecessary diffusion through an opening such as a contact hole increasingly develops problems.
Such problems must be solved for any method of manufacturing a semiconductor device in which a heat treatment is performed after an opening is formed, and the device has a structure containing a diffusible material capable of diffusing through the opening due to heat during the heat treatment.
Incidentally, in FIG. 5, the numerals 31 and 32 indicate conductive films which sandwich a dielectric material (diffusible material 2 in this example) to form a capacitor 3. Further, the abbreviation "Tr" indicates a transistor portion, and particularly in this example, it indicates a MOS transistor. In this specification document, the abbreviation "MOS" is used as a generic term for the structure of conductive material/insulation material-semiconductors, and is not limited to the structure of metal-oxide semiconductors. The numeral 61 indicates an elemental-device-separating region, and specifically, a LOCOS oxide film. The numeral 62 indicates an interlayer insulating film formed on a gate electrode 7 and serving as a component of the transistor Tr. The numeral 63 indicates an interlayer insulating film on the capacitor 3. Identical numerals indicate identical components in all drawings.
As described above, diffusion of a diffusible material can cause various problems in a method for manufacturing a semiconductor device in which a step of forming an opening such as a contact hole and a heat treatment step such as contact annealing are included, and the diffusible material in the device structure may diffuse through the opening due to heat during the heat treatment.